SPI Master Verilog
Designed and implemented SPI Master module with and without chip select.
About this project
The goal was to implement a configurable SPI Master in Verilog that could drive MOSI/MISO lines and optionally control a chip select signal. Clock generation, bit serialization, and CS timing all needed to meet strict setup and hold requirements. I verified correctness using simulation testbenches in ModelSim, comparing waveforms against the SPI protocol spec.
- Configurable clock polarity (CPOL) and phase (CPHA)
- Optional CS variant for multi-device SPI bus
- Verified against SPI spec with ModelSim waveforms
Key features
SPI Master
MOSI/MISO + clock gen
Chip select
Optional CS variant
Verified
ModelSim testbenches
Tech stack
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